1. Field of the Invention
This invention relates to a shift amount detector to determine the shift amount when bit data is shifted for normalization of operation data in arithmetic and logic unit.
2. Description of the Prior Art
In arithmetic and logic operation, data may be shifted for normalization. For example, n (this may be an arbitrary natural number) bits of twos complement data may be normalized by shifting to the left for a certain number of bits. In such a case, a shift amount detecting circuit has been conventionally used to determine the amount of shifting to the left. A conventional shift amount detecting circuit inputs the data as it is if the input data is positive or the data with all bits reversed if it is negative to a bit detecting circuit, which detects the bit position where the bit takes the logical value "1" for the first time. Such a bit detecting circuit checks the values of the data bits starting from the most significant bit and going down to the least significant bit one by one, in order to detect the bit position where the bit value becomes "1" for the first time. The amount of shifting to the left for normalization is determined from the bit position thus detected.
When all bits of an input data consisting of n bits are "1", i.e. the input data is "FFF . . . FH (=1111 . . . 1)" (H indicates that the value is given in hexadecimal notation), the normalization result "100 . . . 0" should be obtained by shifting to the left for (n-1) bits. In a conventional unit, however, since the input data "FFF . . . FH" (+1111 . . . 1) is negative, the value with all data bits reversed ("000 . . . 0H") is input to the bit detecting circuit above. This is the same value as that for input data "000 . . . 0H" and the bit detecting circuit cannot detect the bit position where the bit value becomes "1". This causes the shift amount to the left to be 0. Thus, a conventional unit needed a circuit for exception processing to provide (n-1) as the shift amount to the left irrespective of the detection result by the bit detecting circuit only when input data is "FFF . . . FH".
As described above, conventional unit configuration requires exception processing to provide (n-1) as the shift amount when the input data is "FFF . . . FH". The circuit for this exception processing checks all bits of the input data to see if it is "FFF . . . FH", and when it detects that the data is "FFF . . . FH", it sets the shift amount to the left to (n-1). This complicated processing extends the time required to determine the shift amount, which results in decrease in operation speed at the unit.